RISC-V and FPGA

Figure 1: Running RISC-V Linux inside of the Spike RISC-V processor simulator. Click to enlarge.

Some time ago, the RISC-V project, out of Berkeley, caught my eye. It’s an entirely new instruction set for a microprocessor, along with specific implementations that use it. Notably, unlike *all* other such things, it’s open and free.

Such a thing as an open instruction set, especially when coupled with an open processor reference implementation that works, has been the Holy Grail for open hardware and open software enthusiasts, for a very long time …

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Note: RISC-V is trademarked (but not by this author or site).  Use here is based on this set of terms: https://riscv.org/risc-v-trademark-usage

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About ronaldscheckelhoff

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