RISC-V and FPGA

Figure 1: Running RISC-V Linux inside of the Spike RISC-V processor simulator. Click to enlarge.

Posted 04/26/2017:

Some time ago, the RISC-V project, out of Berkeley, caught my eye.  It’s an entirely new instruction set for a microprocessor, along with specific implementations that use it.  Notably, unlike *all* other such things, it’s open and free.

Such a thing as an open instruction set, especially when coupled with an open processor reference implementation that works, has been the Holy Grail for open hardware and open software enthusiasts, for a very long time. Already, there are products in hard silicon that use this new RISC-V ISA and attendant architecture.  In addition, there’s an implementation meant to run on hardware including FPGA (it’s generically called ‘rocket’), and that is what I’ve been playing with for the past couple days. There is something called the ‘rocket chip generator’ that can create risc-v ‘rocket’ SoC chips. Those seeking more information on such details can check with http://www.riscv.org (website of the RISC-V Foundation).

What’s more specific to my activities, is that I’ve been playing with a refinement of the basic ‘rocket’ implementation – in a project that implements not only the processor (in this case, on FPGA), but the peripherals as well! It’s a basic SoC, untethered, all running on FPGA. The nice thing about the latter project (www.lowrisc.org) is that anyone can play.

The following link shows the difference between a “tethered” and “untethered” implementation:

https://riscv.org/wp-content/uploads/2016/01/Wed1115-untether_wsong83.pdf

The http://www.lowrisc.org project is hosted on github, and can be built and installed in about thirty minutes. That’s all it took to get to the point of running the Spike simulator with the Linux kernel built for RISC-V, as shown in figure one. Unfortunately, Spike is sans peripherals, which defeats part of the purpose. But, if one has an FPGA board, then that can be used to accelerate the fun by a bunch.

I ran into very little trouble building the setup, but I can make a few notes here to help others who want to stick a toe into this pond:

First, the lowrisc implementation is tweaked to run on a couple specific FPGA boards, so my notes here are for running only in Spike. The recommended distro (to use as the build machine) is Ubuntu Trusty, so that’s what I used. For starters, I followed their suggested package(s) installation:

sudo apt-get install autoconf automake autotools-dev curl \
          libmpc-dev libmpfr-dev libgmp-dev gawk \
          build-essential bison flex texinfo gperf \
          libncurses5-dev libusb-1.0-0 libboost-dev git

Next, I got the code and built the toolchain and vmlinux. My notes contain only a part of the build instructions specified on http://www.lowrisc.org and https://github.com/lowrisc – because I culled everything except what it takes to run Linux built for RISC-V in the Spike simulator. The following ‘snips’ are available (Creative Commons licensed) on the aforementioned two sites:

git clone -b untether-v0.2 --recursive https://github.com/lowrisc/lowrisc-chip.git
cd lowrisc-chip
mkdir /home/me/riscv-install
export TOP=/home/me/lowrisc-chip
export RISCV=/home/me/riscv-install
./set_riscv_env.sh
cd $TOP/riscv-tools
./build.sh

cd $TOP/riscv-tools/riscv-gnu-toolchain
rm -rf build
mkdir build
cd build
../configure --prefix=$RISCV
make -j2 linux

cd $TOP/riscv-tools
curl https://www.kernel.org/pub/linux/kernel/v3.x/linux-3.14.41.tar.xz > linux.tar.xz
xz -d linux.xz
tar -xvf linux.tar
cd linux-3.14.41
git init
git remote add origin https://github.com/lowrisc/riscv-linux.git
git checkout -f -t origin/untether-v0.2
make ARCH=riscv defconfig
make ARCH=riscv -j vmlinux
ls -lh vmlinux

Next, I built busybox and root.bin

cd $TOP/riscv-tools
curl http://busybox.net/downloads/busybox-1.21.1.tar.bz2 > busy.tar.bz2
bunzip2 busy.tar.bz2
tar -xvf busy.tar
cd busybox-1.21.1
cp $TOP/riscv-tools/busybox_config .
mv busybox_config .config
make -j2

$TOP/riscv-tools/make_root.sh

Next, I compiled and installed Spike:

cd $TOP/riscv-tools/riscv-isa-sim
mkdir build
cd build
../configure --prefix=$RISCV --with-fesvr=$RISCV --enable-histogram
make -j2
make install

cd $TOP/riscv-tools/riscv-tests/isa
make rv64ui-p-add
spike rv64ui-p-add
echo $?

Finally, I invoked Spike:


spike +disk=busybox-1.21.1/root.bin bbl linux-3.14.41/vmlinux

Figure 2: Invoking Spike simulator

The invocation (above) resulted in what is shown in figure one. Pretty much it all just ‘worked’ – but I did have to delete a build directory, as shown in the toolchain snip. The ‘build’ dir pre-existed, with the result being that the gcc compiler was not built (this manifested itself as ‘cannot find riscv-gcc’ when trying to build vmlinux). Being able to execute with the untethered style should allow for the use of more simple and less expensive FPGA boards. While the boards that the lowrisc project currently targets are not expensive, they do cost more than the SoC/SBC boards in my play bin. I’ve found hardware at https://www.sifive.com that is perhaps more in line with my hobby-level budget. I’ve also considered the parallella board for the purpose at hand. The latter is interesting in other (unrelated) respects.  Are there other boards I should consider?

What I haven’t included in my notes are any installation instructions for the Vivaldo software that is needed to generate the bitstream for the specific real FPGA hardware boards that the lowrisc project has (thus far) targeted.

The original ‘rocket’ RISC-V implementation (AFAIK) relied on a companion processor on the board (usually an ARM A9, etc) – for accessing peripherals and IO. The ‘untethered’ implementation replaces the companion processor with actual peripheral devices on FPGA, creating an untethered SoC that can boot RISCV Linux. There’s some potential in this stuff!


The full guide for development setup is shown at http://www.lowrisc.org/docs/untether-v0.2/dev-env/ – and is where the snippets (listed above) came from. The docs are Creative Commons Attribution ShareAlike 4.0 International Licensed.  This site and author has no affiliation with lowrisc.org


Rocket chip info: https://bar.eecs.berkeley.edu/projects/2014-rocket_chip.html
– ‘Rocket Chip’ is Berkeley’s RISC-V based SOC generator.  Berkeley is also the creator of the RISC-V instruction set.  This site has no affiliation with them.

Note: RISC-V is trademarked (but not by this author or site).  Use here is based on this set of terms: https://riscv.org/risc-v-trademark-usage

The screenshot in figure one shows the output of software that has been released with an open software license. A copy of the licence(s) can be found at: https://github.com/lowRISC/riscv-tools/blob/master/LICENSE


Note: the author does not have a recent, applicable background in circuit building, or battery related issues, so this is presented as the work of a hobbyist, and is not meant for duplication by others. Readers should look elsewhere for design advice and info.

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